This invention relates to analog signal peak detection, and more particularly to an improved peak detection circuit for finding signal minimums and maximums of a signal during the intervals between successive samples in an analog data acquisition system, the improvement making the circuit suitable for implementation in Complementary Metal Oxide on Semiconductor (CMOS) transistor technology.
U.S. Pat. No. 4,271,488 to Saxe for a "High-Speed Acquisition System Employing an Analog Memory Matrix", hereby incorporated by reference, disclosed one version of a high speed analog data acquisition system. Co-pending patent application 07/589,222, now U.S. Pat. No. 5,144,525 by Saxe et al. for an "Analog Acquisition System Including a High Speed Timing Generator", hereby incorporated by reference, describes an improved analog signal acquisition system that is faster than the system described in the '488 patent.
Any method for determining the behavior of an analog signal that is based on sampling the signal at discrete intervals faces the fundamental issue of uncertainty as to the behavior of the signal between samples. The behavior of the signal between samples may nonetheless be of great interest, e.g., if there are glitches on the signal that are causing some sort of problem.
There are digital methods for finding the minimum and maximum behavior of an analog signal, but they also leave gaps between samples and the behavior of the signal within those gaps is still undetermined. However, if the signal can be sufficiently over sampled to ensure capture of the transient events of interest, relatively fleeting events can be captured.
In one of these digital methods, two registers are used to store the output of an analog-to-digital converter. A digital comparator monitors the contents of the two registers and retains, for example, the larger value, while enabling the other register to store the next incoming sample. For a "max" detector, the smaller sample is always discarded and the larger one retained. Thus, the largest value received so far is always saved in one register, while the other register is made available for storing the next incoming value. The result is that the largest value found during a sampling period ends up stored in one or the other of the two registers at the end of the period and that register is then selected for readout. Speed increases can be achieved by interleaving several such max (or min) monitors and selecting the most extreme of their outputs as the maximum-max at the end of the sampling period. However, for signals with very high frequency content sufficient over sampling is either technically infeasible or prohibitively expensive.
FIG. 1 shows a prior art analog peak detection circuit that has been used in analog data acquisition systems to determine signal minimums and maximums. A diode and capacitor are arranged to store the peak output of a differential amplifier whose inputs are the analog input signal to be monitored and the voltage level currently stored on the capacitor. A voltage following amplifier with high input impedance reproduces the voltage level stored on the capacitor as the circuit's output. Such an arrangement, including as it does the use of negative feedback, has been shown to be capable of producing a peak detector that has good linearity and a wide bandwidth when it is properly designed and fabricated using bipolar transistors. When two such circuits are used in alternation, one can be monitoring the signal while the other is being read out and cleared to prepare it for its turn at monitoring the signal.
Complementary Metal Oxide on Semiconductor (CMOS) transistor technology provides some advantages over bipolar transistor technology for some applications. In particular, circuitry implemented in CMOS is less expensive, more dense, and uses less power than comparable circuitry implemented in bipolar transistors. However, CMOS transistors are slower than bipolar ones, have lower gain, and must be configured differently in order to achieve linear high bandwidth operation.
Co-pending U.S. patent application 07/844,089 by Kogan for a "CMOS-Based Peak Detector for Fast-In, Slow-Out Min/Max Detection", hereby incorporated by reference, discloses several approaches to min/max peak detection that utilize CMOS circuitry. These approaches produce less than ideal results because diode substitutes implemented in CMOS do not perform like ideal diodes, and this causes input signal and time dependent inconsistencies in the performance of the circuit.
An ideal diode conducts only when the voltage across it is greater than a conduction threshold, and does not conduct at all when the applied voltage is less than that amount. Less than ideal diodes, including diode substitutes implemented in CMOS, continue to conduct, but in decreasing amounts, as the voltage across them is decreased, instead of having a sharp cutoff at a specific voltage. This means that the stored maximum voltage can continue to change over the sample interval, with the change being a function of both the voltage across the "diode" and the duration of the time that it is present. This also leads to the partial loss of small fast signals, which may not cause sufficient "diode" conduction to be detected, or which may be swamped by time and signal dependent leakage effects. A CMOS-compatible approach to peak detection that successfully avoids these time and signal dependencies is therefore needed.
The circuits shown in the Kogan 07/844,089 application also introduce a non-linearity into the peak detection process. It would also be desirable to eliminate such non-linearities to the maximum extent possible, even though they can be compensated for by the addition of linearizing means in the downstream signal path.